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Events, English
VLSI Design Technical Committee (VLD) / RECONF 2026 — Corporate Exhibition with Two Live Demos
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Events, English
Events, English
New Technology Exchange Meeting 2025 — Tokyo Metropolitan Small & Medium Enterprise Support
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Events, English
Events, English
Exhibited at EdgeTech+ 2025 (Efinix® Booth)
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Events, English
Media, English
Interface Magazine — Trinita® 1-Stage RISC-V Core Featured in FPGA Magazine Special Edition No.4
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Media, English
Events, English
EdgeTech+ 2024 — Exhibited at Efinix® Booth
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Events, English
Events, English
New Technology Exchange Meeting 2024 — Tokyo Metropolitan Small & Medium Enterprise Support
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Events, English
Events, English
JASA RISC-V Webinar #19 — Trinita® 1-Stage RISC-V Core Technical Presentation
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Events, English
GitHub, English
Trinita® 1-Stage RISC-V Core Now Available for Efinix® Trion® T8 (Xyloni)
GitHub, English
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GitHub, English
Media, English
KAGA DEVICES — Trinita® 1-Stage RISC-V Core Power Efficiency Improved: 2.1× (T20) / 1.8× (Ti60) vs. VexRiscv
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Media, English
Papers, English
SASIMI 2024 — Energy Reduction of Health Monitoring Processor by Optimizing Supply and Back-Gate Voltages with Simulated Annealing
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Papers, English
GitHub, English
Trinita® 1-Stage RISC-V Core (RV32IM) Now Available on GitHub — Free Evaluation for Efinix® Sapphire SoC
GitHub, English
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GitHub, English
GitHub, English
SpO2 Demo Design Released — Featuring Power-Optimized Trinita® 1-Stage RISC-V Core
GitHub, English
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GitHub, English
R&D, English
Improved ASIC Prototype Complete — Trinita® 1-Stage RISC-V Core in ROHM 180nm Process (Joint Research with Hirosaki University)
R&D, English
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R&D, English
R&D, English
ASIC Prototype Complete — Trinita® 1-Stage RISC-V Core in Renesas SOTB 65nm Process (Joint Research with Hirosaki University)
R&D, English
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R&D, English
Events, English
RISC-V Days Tokyo 2022 Spring — Joint Presentation with Efinix®, Inc.
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Events, English
R&D, English
ASIC Prototype Complete — Trinita® 1-Stage RISC-V Core in ROHM 180nm Process (Joint Research with Hirosaki University)
R&D, English
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R&D, English
Media, English
Innovations-i Interview — Pursuing the Ultimate Low-Power Single-Stage LSI
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Media, English
Media, English
Innovation Business Award 2021 — UNO Laboratories Receives "Yoi Shigoto Okoshi Award" for Energy-Efficient Processor Development
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Media, English
Papers, English
IEEE GCCE 2021 — An Energy Efficient Processor Applicable to Continuous SpO2 Monitoring
Papers, English
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Papers, English
R&D, English
High-Efficiency Operation Verified — Trinita® 1-Stage RISC-V Processor Implemented on Efinix® Trion® T20 (SMIC 40nm)
R&D, English
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R&D, English
Media, English
MONOist — Non-pipelined Single-Stage RISC-V Processor Doubles FPGA CPU Clock Efficiency
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Media, English
Media, English
Press Release — Development of Highly Efficient Single-Stage RISC-V Processor for Energy Harvesting IoT Devices
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Media, English
Papers, English
SASIMI 2021 — Energy Efficient RISC-V Processor for Portable Sensor Applications
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Papers, English
R&D, English
UNO Laboratories Joins RISC-V International as Silver Member (Strategic Member)
R&D, English
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R&D, English
Papers, English
IEEE MWSCAS 2019 — A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck
Papers, English
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Papers, English