Improved ASIC Prototype Complete — Trinita® 1-Stage RISC-V Core in ROHM 180nm Process (Joint Research with Hirosaki University) R&D, EnglishMasami FukushimaSeptember 30, 2023RISC-V, RV32IM, ROHM, ASIC, Trinita
ASIC Prototype Complete — Trinita® 1-Stage RISC-V Core in Renesas SOTB 65nm Process (Joint Research with Hirosaki University) R&D, EnglishMasami FukushimaOctober 31, 2022RISC-V, Trinita, ASIC, Hirosaki University, Renesas
ASIC Prototype Complete — Trinita® 1-Stage RISC-V Core in ROHM 180nm Process (Joint Research with Hirosaki University) R&D, EnglishMasami FukushimaFebruary 28, 2022RISC-V, RV32IM, ASIC, Hirosaki University, ROHM
High-Efficiency Operation Verified — Trinita® 1-Stage RISC-V Processor Implemented on Efinix® Trion® T20 (SMIC 40nm) R&D, EnglishMasami FukushimaOctober 29, 2021RISC-V, FPGA, Trinita, Efinix, Sapphire SoC
UNO Laboratories Joins RISC-V International as Silver Member (Strategic Member) R&D, EnglishMasami FukushimaFebruary 28, 2020RISV-C International, Strategic Member, UNO Laboratories, RISC-V
