ASIC Prototype Complete — Trinita® 1-Stage RISC-V Core in Renesas SOTB 65nm Process (Joint Research with Hirosaki University) R&D, EnglishMasami FukushimaOctober 31, 2022RISC-V, Trinita, ASIC, Hirosaki University, Renesas
ASIC Prototype Complete — Trinita® 1-Stage RISC-V Core in ROHM 180nm Process (Joint Research with Hirosaki University) R&D, EnglishMasami FukushimaFebruary 28, 2022RISC-V, RV32IM, ASIC, Hirosaki University, ROHM
SASIMI 2021 — Energy Efficient RISC-V Processor for Portable Sensor Applications Papers, EnglishMasami FukushimaApril 1, 2021RISC-V, Trinita, SASIMI, Hirosaki University, FPGA
