KAGA DEVICES — Trinita® 1-Stage RISC-V Core Power Efficiency Improved: 2.1× (T20) / 1.8× (Ti60) vs. VexRiscv Media, EnglishMasami FukushimaMay 10, 2024RISC-V, RV32IM, Trinita, Kaga Devices, Efinix
SASIMI 2024 — Energy Reduction of Health Monitoring Processor by Optimizing Supply and Back-Gate Voltages with Simulated Annealing Papers, EnglishMasami FukushimaMarch 25, 2024RISC-V, RV32IM, Trinita, ASIC, ROHM
Trinita® 1-Stage RISC-V Core (RV32IM) Now Available on GitHub — Free Evaluation for Efinix® Sapphire SoC GitHub, EnglishMasami FukushimaMarch 14, 2024RISC-V, Trinita, Efinix, Free Evaluation, Sapphire SoC
SpO2 Demo Design Released — Featuring Power-Optimized Trinita® 1-Stage RISC-V Core GitHub, EnglishMasami FukushimaMarch 14, 2024RISC-V, Trinita, Github, Free Evaluation, SpO2
Improved ASIC Prototype Complete — Trinita® 1-Stage RISC-V Core in ROHM 180nm Process (Joint Research with Hirosaki University) R&D, EnglishMasami FukushimaSeptember 30, 2023RISC-V, RV32IM, ROHM, ASIC, Trinita
ASIC Prototype Complete — Trinita® 1-Stage RISC-V Core in Renesas SOTB 65nm Process (Joint Research with Hirosaki University) R&D, EnglishMasami FukushimaOctober 31, 2022RISC-V, Trinita, ASIC, Hirosaki University, Renesas
RISC-V Days Tokyo 2022 Spring — Joint Presentation with Efinix®, Inc. Events, EnglishMasami FukushimaJune 30, 2022RISC-V, Efinix, FPGA, Trinita, Presentation
ASIC Prototype Complete — Trinita® 1-Stage RISC-V Core in ROHM 180nm Process (Joint Research with Hirosaki University) R&D, EnglishMasami FukushimaFebruary 28, 2022RISC-V, RV32IM, ASIC, Hirosaki University, ROHM
